Projects

A collection of personal projects, experiments, and practical work across CPU microarchitecture, hardware verification, and RTL design.

Computer architecture and performance

Out-of-order RISC-V core model with value prediction — a squash-triggered selective filter on top of stride value prediction, lifting harmonic-mean IPC 22.5% across 15 SPEC benchmarks within a 32 KB storage budget
Configurable cache and memory hierarchy simulator — 112 simulations of design-space exploration; L1/L2 co-optimization cut average access time 11.7%, and stream buffers dropped miss rate from 25% to 0.1%
Branch predictors: bimodal, gshare and hybrid — gshare cut gcc misprediction from 11.17% to 6.37% where bimodal had saturated and could not improve at any table size
Out-of-order instruction scheduling simulator — a nine-stage superscalar pipeline across 88 design points, showing issue-queue requirements doubling with each doubling of width
Cache-aware domain decomposition in OpenMP — 2D blocking beat row-major decomposition by 15% on a single thread, before any parallel speedup

UVM verification environment for a pipelined LC-3 — instruction-level architectural checking against a reference model, targeting the pipeline’s stall and bypass paths (in progress)
SystemVerilog verification environment for an I2C master — 4 covergroups over 18 coverpoints mapped to a 22-item verification plan, closed to 100% register coverage

Pipelined CNN accelerator RTL — five-stage convolution datapath performing 16 multiply-accumulates per cycle, with line buffering and burst DRAM streaming
RTL design blocks — LRU replacement, skid buffers, arbiters, priority encoders, credit-based flow control, and timing-optimization problems