RISC-V

RISC-V

RISC-V is an open instruction set architecture (ISA). The ISA defines the contract between software and a processor; it does not prescribe how a particular processor must be built internally.

This section studies RISC-V implementations from a computer-architecture perspective: pipelines, out-of-order execution, instruction scheduling, memory systems, vector execution, and performance–power–area tradeoffs.

Paper studies

• Cuzco: scheduling the future in a high-performance RISC-V core

Useful foundations

• RVA23 application-processor profile
• RISC-V Vector Extension