<?xml version="1.0" encoding="utf-8"?><feed xmlns="http://www.w3.org/2005/Atom" ><generator uri="https://jekyllrb.com/" version="3.10.0">Jekyll</generator><link href="http://bharadwajsudula.com/feed.xml" rel="self" type="application/atom+xml" /><link href="http://bharadwajsudula.com/" rel="alternate" type="text/html" /><updated>2026-08-18T16:17:39+00:00</updated><id>http://bharadwajsudula.com/feed.xml</id><title type="html">Bharadwaj Sudula</title><subtitle>Notes on SystemVerilog, UVM, Computer Architecture, and more</subtitle><entry><title type="html">Welcome</title><link href="http://bharadwajsudula.com/sv/2026/08/18/welcome.html" rel="alternate" type="text/html" title="Welcome" /><published>2026-08-18T00:00:00+00:00</published><updated>2026-08-18T00:00:00+00:00</updated><id>http://bharadwajsudula.com/sv/2026/08/18/welcome</id><content type="html" xml:base="http://bharadwajsudula.com/sv/2026/08/18/welcome.html"><![CDATA[<p>Welcome to my site. I’ll be posting notes on SystemVerilog, UVM, and computer architecture here.</p>]]></content><author><name></name></author><category term="sv" /><summary type="html"><![CDATA[Welcome to my site. I’ll be posting notes on SystemVerilog, UVM, and computer architecture here.]]></summary></entry></feed>